1. Field of the Invention
The present invention relates to methods for the production of two-transistor electrically erasable programmable read only memory (EEPROM) cells and, in particular, to a method of fabricating such a cell utilizing a self-aligned stacked gate etch.
2. Description of the Related Art
An electrically programmable read only memory (EPROM) device is a non-volatile memory integrated circuit which is used to store binary data. Power can be removed from an EPROM without loss of data. That is, upon reapplying power, the originally stored binary data is retained.
In addition to its data retention capability, an EPROM can also be programmed to store new binary data. Reprogramming is accomplished by first exposing the EPROM to an ultraviolet (UV) light source in order to erase the old binary data. A UV-transparent lid on the packaged EPROM chip allows this erasure to occur. Following erasure, the new binary data is written into the EPROM by deactivating the chip select line in order to switch the EPROM's data outputs to inputs. The EPROM address inputs are then set to a starting value, the desired data is connected to the data inputs and the data is written into the data storage register identified by the address inputs. The address inputs are then incremented and the cycle is repeated for each storage register in the EPROM array.
In an EPROM read operation, the binary data stored in the data storage register identified at the address inputs is connected to the chip's data output buffers. If the EPROM's chip select signal is activated, then the binary data from the selected storage register is provided to the databus.
An electrically erasable programmable read only memory (EEPROM) device is a variation of the EPROM design wherein binary data is read, written and erased electrically. A single operation erases a selected data storage register.
A conventional two-transistor EEPROM device 10 is illustrated schematically by its circuit equivalent in FIG. 1. Access transistor 12 is used for cell selection and a non-volatile memory (NVM) storage transistor 14, which includes a word line control gate 16 and a floating gate 18, is used for charge storage.
FIGS. 2 and 3 illustrate a conventional two-transistor EEPROM device 10 in layout and cross-sectional views respectively. The device includes an access transistor gate 20 that is insulated from underlying P-type silicon substrate 22 by insulating layer 24 (typically silicon dioxide). The device also includes a floating gate 26, which is insulated and separated from silicon substrate 22 by insulating layer 24. A portion of floating gate 26 is separated from silicon substrate 22 by a relatively thin portion of insulating material 28. This relatively thin portion of insulating material, when made of silicon dioxide, is commonly known as "tunnel" oxide. A word line control gate 30 overlaps floating gate 26, but is separated from floating gate 26 by interpoly insulator 32 (typically an oxide-nitride-oxide (ONO) composite layer). Device 10 also includes a buried N+ region 34 underneath tunnel oxide 28, as well as N+ source region 36, combined N+ source/drain region 38 and graded N-type drain 40. A contact 42 is made to graded N-type drain 40.
In conventional processes used for fabricating the two-transistor EEPROM cell of FIGS. 2 and 3, the floating gate 26 is patterned from the first polysilicon (poly 1) layer deposited, while the word line control gate 30 and access transistor gate 20 are patterned from the second polysilicon (poly 2) layer deposited. Furthermore, in a conventional two-transistor EEPROM, the poly 2 word line control gate is formed such that it overlaps the poly 1 floating gate by an amount which insures a good coupling factor between the poly 2 word line control gate and the poly 1 floating gate. This overlap is illustrated by dimension L in FIGS. 2 and 3. To compensate for potential misalignment between the poly 2 word line control gate and the poly 1 floating gate, the cell size must be increased in the horizontal direction of FIG. 3. This approach, however, has the drawback of producing relatively large cell areas and relatively low cell packing density.
The drawbacks created by potential misalignment between the poly 2 word line control gate and the poly 1 floating gate can be solved by taking advantage of the fact that two of the poly 1 floating gate edges are parallel to the poly 2 word line control gate edges. The solution would employ a self-aligned stacked gate etch process to define these edges. The resultant structure, upon employment of a self-aligned stacked gate etch in conventional processes, is illustrated in FIG. 4. In FIG. 4, the edges of the poly 1 floating gate 42, that are parallel to the poly 2 word line control gate 40, are self-aligned to the edges of the poly 2 word line control gate 40. Interpoly insulator 44 separates poly 2 word line control gate 40 from poly 1 floating gate 42. Poly 2 access transistor gate 46 is insulated from silicon substrate 48 by insulating layer 50. Since poly 1 floating gate 42 is self-aligned to poly 2 word line control gate 42, there is no overlap L as in the conventional structure of FIGS. 2 and 3.
Self-aligned stacked gate etches have been described in U.S. Pat. Nos. 5,240,870 and 5,371,030 to Bergemont, both of which are hereby fully incorporated by reference. The methods described in these patents are useful, but require additional processing steps, including a differential oxidation, to avoid trenching of exposed silicon substrate regions during the self-aligned stacked gate etch step. The areas on either side of an access transistor 52 and an NVM storage transistor 54 would be subject to undesirable trenching in a conventional self-aligned stacked gate etch, as illustrated in FIG. 5.
Still needed in the art is a process of fabricating a two-transistor EEPROM cell with a self-aligned NVM storage transistor that eliminates the risk of trenching in the regions between the access transistor and the NVM storage transistor and that provides for increased cell densities.